A core (e.g., a hard core logic module with fixed netlist, fixed gate placement and routing, etc.) may be used in different top level (e.g., chip-level, etc.) design integration processes (e.g., chip level signal routing, power routing, metal utilization, etc.). The core (e.g., the core logic module) level routing (e.g., a signal route, a clock route, a power route, and/or an additional metallization) on a chip may take up a bottommost layers (e.g., a bottom three layers, etc.) of the chip. The top level (e.g., chip-level) routing (e.g., a signal route, a clock route, a power route, and/or an additional metallization) may take up a remaining layers (e.g., top 4-8 layers, etc.).
A core timing model (CTM) of the core may represent path delays from core inputs to core outputs. The core timing model (CTM) of the core is built before a top level integration process (e.g., chip level signal routes, clock routes, power routes, and/or additional metallization, etc.) during which the top level routing is integrated with the core. Hence, parasitic effects (e.g., a cross-talk and a capacitive coupling, etc.) on the core caused by the top level signal routing (e.g., an over-core routing) may not be captured by the core timing model (CTM). By not capturing the parasitic effects in the core timing model, inaccuracies pertaining to a prediction of parasitic effects (e.g., a delay inaccuracy, a timing failure, and/or a corrupt signal, etc.) may be introduced.
As such, a number of procedures may need to be carried out during a core timing model generation process to remedy these inaccuracies. For example, a delay prediction range may need to be increased after the core timing model generation for each design to account for any potential effects (e.g., cross-talk, and capacitive coupling, etc.) due to the top level signal routing (e.g., chip level signal routes, clock routes, power routes, etc.) and/or an additional metallization process during fabrication. In addition, a flat delay prediction and extraction may need to be accomplished at the top level (e.g., extraction that will extract chip and core level signal routes, clock routes, power routes, additional metallization, etc.) before performing timing analysis.
However, the assumption may be a poor representation of the actual top level signal routing situation resulting in more inaccuracies. Transferability of the same core timing model to other applications may also be compromised due to differences in potential effects (e.g., cross-talk, and capacitive coupling, etc.) resulting from different top level (e.g., chip-level) routing. Moreover, these complications may be further aggravated in a design with the over-core routing (e.g., top level routing that may occupy a layer directly above and/or under (e.g., adjacent to) the core level routing during the top level integration process).
In addition, the top level integration process that omits a layer directly adjacent (e.g., directly above and/or directly under) to the outermost layer carrying the core level routing (e.g., chip level signal routes, clock routes, power routes, and/or additional metallization, etc.) places many top-level wires in regions due to avoiding over-core routing. However, by not performing over-core routing during the top level (e.g., chip-level, etc.) integration process (e.g., chip level signal routes, clock routes, power routes, and/or additional metallization, etc.), valuable chip space adjacent to the core may be wasted while aggravating congestion in other regions of the chip. A longer route (e.g., cannot use straight paths, etc.) may be required as a result of avoiding regions adjacent to (e.g., directly above and/or directly below) the core. The longer signal route could potentially drastically decrease performance (e.g., decrease an operating frequency and/or increase interconnect delay, etc.). An additional complication may be introduced in satisfying timing constraints due to reduced flexibility in top level routing (e.g., chip level signal routing, clock routing, power routing, and/or additional metallization, etc.).